Computer Architecture Week 4 NPTEL Assignment Answers 2025

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✅ Subject: Computer Architecture
📅 Week: 4
🎯 Session: NPTEL 2025 July-October
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NPTEL Computer Architecture Week 4 Assignment Answers 2025

1. Which of the following ARM branch instructions test the Zero flag (Z) to determine whether to branch or not? Choose the most appropriate answer.

• B label
• BEQ label
• BNE label
• Both BEQ and BNE

Answer : See Answers

2. You’re writing an ARM assembly routine to compute the factorial of a positive integer (>,1) stored in R2; the result will be saved in R3. You initialize and loop as follows:

MOV R3, #1
MOV R4, #1
.loop:
MUL R3, R3, R4
ADD R4, R4, #1
CMP R4, R2
__ .loop

Which branch suffix should replace ___________ so that the loop continues while i ≤ n?

• BGT (Greater Than)
• BLT (Less Than)
• BLE (Less or Equal)
• BGE (Greater or Equal)

Answer :

3. In ARM assembly, what is the preferred instruction to return from a function, and why?

• MOV PC, LR – because it works on all ARM architectures
• BX LR – because it supports switching between ARM and Thumb states
• B LR – because it is faster than BX
• POP {PC} – because it automatically restores flags

Answer :

4. In ARM assembly, consider the following instructions used to access an array and increment the index:

LDR R3, [R0, R2, LSL #2]
ADD R2, R2, #1

Which of the following fused instructions attempts to perform load and address update in one step, and what does it effectively do?

• LDR R3, [R0], R2, LSL #2 — loads from [R0 + R2 << 2], then updates R0
• LDR R3, [R0, R2], LSL #2 — illegal syntax in ARM
• LDR R3, [R0, R2, LSL #2]! — loads and writes back updated address to R0
• LDR R3, [R0, R2, LSL #2] — also updates R0 after load

Answer :

5. In ARM assembly, which pair of instructions is typically used to preserve and restore multiple registers across a function call (i.e., in the function prologue and epilogue)?

• STMIA to save, LDMDB to restore
• LDMFD to save, STMFD to restore
• STMFD to save, LDMFD to restore
• PUSH to save, POP to restore — only available in Thumb mode

Answer :

6. In ARM instruction encoding, which of the following immediate values requires a rotation to be representable in the 12-bit immediate field of a data-processing instruction?

• 0x0000002A
• 0x2A000000
• 0x000002A0
• 0x00000020

Answer : See Answers

7. Which of the following statements correctly describes the x86 flags and registers, in comparison to a SimpleRISC-like architecture?

• The flags register is always 64 bits wide and is called EFLAGS.
• The instruction pointer is called PC, and it has only a 32-bit variant.
• The x86 architecture uses EFLAGS/RFLAGS for condition flags and has 16, 32, and 64-bit variants.
• The instruction pointer is called LR and stores the link address after branching.

Answer :

8. Which of the following is true about the segment registers in the x86 architecture?

• x86 has 4 segment registers, each 32 bits wide.
• The FS and GS segment registers are only used in 64-bit mode.
• x86 has 6 segment registers (CS, DS, SS, ES, FS, GS), each 16 bits wide.
• Segment registers are used to store general-purpose data values.

Answer :

9. Which of the following is a valid example of x86 memory direct addressing using a base, scaled index, and displacement?

• [EBX]
• [4ECX + 8]
• [EBX + ECX4 + 8]
• [EAX + EBX + ECX]

Answer :

10. Which of the following register sets corresponds to the 64-bit version of the x86 architecture?

• AX, BX, CX, DX, SP, BP, SI, DI
• EAX, EBX, ECX, EDX, ESP, EBP, ESI, EDI
• RAX, RBX, RCX, RDX, RSP, RBP, RSI, RDI, R8–R15
• A0, B0, C0, D0, SP, BP, SI, DI

Answer : See Answers