Computer Architecture Week 3 NPTEL Assignment Answers 2025

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✅ Subject: Computer Architecture
📅 Week: 3
🎯 Session: NPTEL 2025 July-October
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NPTEL Computer Architecture Week 3 Assignment Answers 2025

1. In a typical function call stack, which of the following is not usually part of an activation block?

• Return address
• Saved frame pointer
• Local variable space
• Instruction cache contents

Answer : See Answers

2. What happens when a program’s call stack exceeds its allocated size (stack overflow)?

• The CPU automatically doubles the stack memory.
• The program’s return address is corrupted, often causing a crash or undefined behavior.
• The operating system switches to a new stack silently.
• All local variables are zeroed out and execution continues.

Answer :

3. An instruction with I-bit = 1, rd = x5, rs1 = x2, imm = 0xFF, modifier = 01 performs which of the following?

• ADD x5, x2, 0xFF treating 0xFF as a signed (two’s-complement) immediate
• ADD x5, x2, 0xFF treating 0xFF as an unsigned zero-extended immediate
• SUB x5, x2, 0xFF with half-precision modifier (“h”)
• AND x5, x2, 0xFF with default modifier

Answer :

4. Which of the following SimpleRISC instructions updates the condition flags but does not write any result to a destination register?

• CMP rs1, rs2
• NOT rd, rs1
• MOV rd, rs1
• ADD rd, rs1, rs2

Answer :

5. Consider a regular store instruction:

st rd, imm[rs1]

what does the rd field represent?

• The base register for calculating the store address
• The source register containing the data to be stored
• The destination register where loaded data would go
• Additional bits of the immediate offset

Answer :

6. MOV r0, #4
ADD r0, r0, #5
SUB r1, r0, #19

After executing the above ARM assembly code, what value will be present in register r1?

• –10
• 10
• 18
• –18

Answer : See Answers

7. MOV r1, #1 ; A = 1
MOV r2, #0 ; B = 0
AND r3, r1, r2
MVN r0, r3

After executing the above ARM assembly code, which signed 32-bit value will be in register r0 (i.e., computing NOT(A AND B)?

• 0
• 1
• -1
• Undefined

Answer :

8. MOV r1, #3 ; operand1 = 3
MOV r2, #5 ; operand2 = 5
SUBS r0, r1, r2 ; r0 = 3 – 5, flags updated

After executing the above ARM assembly code, what value will the C (carry) flag in the CPSR hold?

• 0
• 1
• Undefined
• Unchanged

Answer :

9. MOV r1, #0
MOV r2, #0
SUBS r3, r1, r2
MOV r5, #10
MOV r4, #5
SBC r6, r5, r4

After executing the above ARM assembly code, what value will be in register r6?

• 4
• 5
• 6
• 10

Answer :

10. MOV r1, #0xF0
MOV r2, #0xCC
EOR r3, r1, r2

After executing the above ARM assembly code, what will be the hex value stored in register r3?

• 0x3C
• 0xFC
• 0x00
• 0xFF

Answer : See Answers